Digital processing of audio and visual information is central to a growing number of consumer electronics products.  In computing, it has been spurred by Internet access through cable modems, fast phone lines, and radio.  One result is a larger role for fast, programmable digital signal processor (DSP) chips, and a lengthening menu of such components from which system designers may choose.

Our guest speaker, Jeff Bier, specializes in DSP evaluation and software development.  He will survey the latest design trends in processors for DSP: VLIW (very long instruction word) and superscalar architectures, enhanced conventional DSP architectures, and SIMD (single instruction, multiple data) extensions.  He'll identify the key technical features of these approaches and highlight their comparative advantages and disadvantages. 

Mr. Bier will also discuss the issue of how to fairly measure the DSP performance of these different architectures, and illustrate this discussion with representative benchmark results.  He'll then examine the ways in which increasing levels of integration affect the use and development of processors for DSP, including the growing importance of DSP cores and the expanding array of hybrid DSP/microcontrollers. 

Jeff Bier is General Manager and co-founder of Berkeley Design Technology, Inc. (BDTI), a DSP technology analysis and software development firm.  There he supervises the evaluation and benchmarking of DSP processor designs and oversees the development of DSP software.  Mr.
Bier is a member of the IEEE Design and Implementation of Signal Processing Systems (DISPS) Technical Committee.  His engineering degrees are from Princeton University and the University of California at Berkeley.live, interactive broadcasts on the Internet. 

A DSP application takes a signal from or to the physical environment and processes the information in a computer.  There are a very large number of these applications and it is increasingly hard to find electronic devices that don't use DSP.  Typical DSP applications process large amounts of data at high rates.  The algorithms used are data intensive, but repetitive, and parallelism can be used.  Accuracy and real time processing requirements can be high.  Architectures for DSP include baseline conventional DSPs, VLIW (Very Long Instruction Word), Superscalar, General Purpose Processors, and Hybrids.  

Conventional processors use 16- to 32-bit instructions with one instruction per cycle, and use fixed-point processors.  Mass marketed DSP products use 16-bit processors because they are cheap, but they do require complex programming and have highly constrained architectures.  Texas Instruments provided an early DSP in 1982 and until recently there has been little change in the architectures.  The conventional processors were programmed in assembly language and only a limited number of operations can be placed in a 16-bit instruction.  Compilers have been improved and "mostly" generate accurate code.  Past difficulties with inaccurate code output have made programmers reluctant to use compilers.  

The "Conventional DSPs" use dedicated hardware for addressing, loops, and execution control and have multiple access on-chip memory.  They are designed for low cost, low power consumption, and low memory usage.  Recently the conventional DSP architectures have been enhanced with more parallelism; additional specialized hardware and the addition of
co-processors.  The enhancements provide performance increases while maintaining low cost, low power consumption and code density.  They are either compatible with early process-ors or similar to them.   However, they are increasingly complex and hard to program.  It is difficult to produce compilers for them and it is questionable how much further we can go with this approach.  

Two newer approaches are Superscalar and Very Long Instruction Word (VLIW).  Superscalar DSP puts very complicated hardware on a chip.  VLIW has simpler hardware, but makes it the responsibility of the programmer to specify the parallelism.

So far, the trend has been toward VLIW as opposed to Superscalar.  Currently VLIW has up to eight 32-bit instructions in a 256-bit word and provides more regular, orthogonal, RISC-like operations with large, uniform register sets.  It runs fast, and its more regular architecture is potentially easier to program and a better target for compilers, and there is the promise of scalability.  Disadvantages are that it provides a new type of programmer/compiler complexity, as the programmer must keep
track of instruction scheduling.  The "potential" of easier programming may take some effort to be achieved.  Code size is large and there are high program memory bandwidth requirements, as well as high power consumption.  

Superscalar architectures issue multiple instructions per instruction cycle, have a RISC-like instruction set, and lots of inherent parallelism.  Compared to conventional processors, they provide a large jump in performance, and have more regular architectures.  The programmer doesn't have to worry about instruction scheduling, and the code size is not increased significantly.  However, energy consumption is a major challenge and dynamic behavior complicates software development.
Execution-time variability can be a hazard and code optimization is challenging.  Mr. Bier commented that all major processor vendors are moving toward VLIW for DSPs.  

Next Mr. Bier described what he called "The GPP Threat" because high-performance general- purpose processors for PCs and workstations (MMX Pentium and PowerPC with AltiVec) are increasingly suitable for DSP tasks.  They have higher clock rates than most DSPs, they are already present in PCs, have strong tool support for major processors, and their cost-performance can rival floating-point DSPs.  Disadvantages are unpredictable execution times leading to possible real-time application problems, difficulty in developing optimized DSP code, high power consumption and poor cost-performance compared to fixed-point DSPs.  General purpose processors for embedded applications are beginning to address DSP needs.

One example is increased performance of video games.  GPPs have respectable DSP and cost performance but there is a high degree of programming complexity required, and there are not many tools provided for DSP purposes.   Mr. Bier showed some performance data.  A 266 MHz Pentium showed respectable performance but had the worst power
consumption and did not compare well on cost-performance with most of the DSPs.   

He concluded that there is increased diversification of architectures and that performance measurement is becoming harder, not easier.  Integration of cores and the ability to quickly generate custom processor-based devices will be most important.  Tools may become more critical than architectures.  Ease of development of efficient code is key.  

This, the sixth meeting of the year - attended by 35 people, was an interesting and educational meeting with an excellent presentation by Jeff Bier.  If you either missed the meeting or want additional information on the topic go to  http://www.bdti.com.  Information can also be obtained from the textbook "DSP Processor Fundamentals" (BDTI,1996) and
the paper "The BDTImark:  A Measure of DSP Execution Speed" (BDTI,1997).  They can be reached by e-mail at info@BDTI.com.